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Adapted from “Virtuoso AMS Environment User Guide” by Cadence The mixed-signal design flow uses Cadence Virtuoso AMS environment and a set of tools tuned to facilitate the development of mixed-signal designs. The Virtuoso AMS environment and simulator work together to enable you to netlist, compile, elaborate, and simulate a circuit that contains analog, digital, and mixed-signal components. The AMS environment consists of the AMS netlister and AMS Design Prep.

The former translates Cadence database access (CDBA) cellviews in your design to Verilog®-AMS netlists, and the latter prepares your design for simulation by letting you manage the global signals and design variables in your design and by ensuring that the netlists are up to date and compiled for elaboration. The AMS simulator provides both the Spectre and the UltraSim solvers and you can switch back and forth between them as your design evolves. In this following tutorial, an example of using the AMS environment and simulator to netlist, compile, elaborate, and simulate the top schematic, which contains analog, digital, and mixed-signal components is given step by step.